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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc33897 rev. 16.0, 6/2007 freescale semiconductor technical data ? freescale semiconductor, inc., 2006 - 2009. all rights reserved. single wire can transceiver the 33897 series provides a physical layer for digital communications purposes using a carrier sense multiple access/ collision resolution (csma/cr) data link operating over a single wire medium. this is more commonly referred to as single wire controller area network (can). the 33897 series operates directly from a vehicle's 12 v battery system or a broad range of dc-power sources. it can operate at either low or high (33.33 kbps or 83.33 kbps) data rates. a high- voltage wake-up feature allows t he device to control the regulator used in support of the mcu and other logic. the device includes a control terminal that can be used to put the module regulator into sleep mode. the presence of a defined wake-up voltage level on the bus will reactivate the control line to turn the regulator and the system back on. the device complies with the gmw3089v2.4 general motors corporation specification. features ? waveshaping for low electrom agnetic interference (emi) ? detects and automatically handles loss of ground ? worst-case sleep mode current of only 60 a (75 a on the 33897t) ? current limit prevents damage due to bus shorts ? built-in thermal shutdown on bus output ? protected against vehicular electrical transients ? undervoltage lockout prevents false data with low battery ? pb-free packaging designated by suffix code ef ordering information contains lead pb-free rohs temperature range (t a ) package mc33897d/r2 mc33897ad/r2 mc33897ef/r2 mc33897aef/r2 mcz33897ef/r2 mcz33897tef/r2 mcz33897aef/r2 *mcz33897cef/r2 - 40c to 125c 14 soicn mc33897bef/r2 mcz33897bef/r2 *mcz33897def/r2 8 soicn *recommended device for all new designs single wire can transceiver 33897/a/b/c/d/t d suffix ef (pb-free) suffix 98asb42565b 14-terminal soicn ef (pb-free) suffix 98asb42564b 8-terminal soicn
analog integrated circuit device data 2 freescale semiconductor 33897/a/b/c/d/t figure 1. 33897/a/c simpli fied application diagram figure 2. 33897b/d simplified application diagram mcu 33897/a/c/t power source battery swc bus txd bus mode0 load mode1 vbatt rxd cntl gnd vcc en vcc 4 voltage regulator mcu 33897b/d battery swc bus txd bus mode0 load mode1 vbatt rxd gnd vcc vcc
analog integrated circuit device data freescale semiconductor 3 33897/a/b/c/d/t device variations device variations *recommended device for all new designs table 1. device variations part no. load voltage sleep mode other significant differences see page 33897 1.0 v max ? 14-pin package 8 33897t ? 14-pin package ? quiescent current in sleep mode, 5.0v v |? 13v, typical - 55 a, max - 75 a ? esd voltage: machine model 100v 6 , 7 , 8 33897a 0.1 v max ? 14-pin package ? removes diode drop during sleep mode ? may not detect loss of ground under certain module characteristics. 8 33897b ? 8-pin package ? removes diode drop during sleep mode ? does not include the cntl terminal ? may not detect loss of ground under certain module characteristics. 2 , 4 , 6 , 7 , 8 , 13 , 16 *33897c ? 14-pin package ? removes diode drop during sleep mode ? effectively detects loss of ground ? esd voltage: human body model 1500v, machine model 100v 8 *33897d ? 8-pin package ? removes diode drop during sleep mode ? effectively detects loss of ground ? does not include the cntl terminal ? esd voltage: human body model 1500v, machine model 100v 2 , 4 , 6 , 7 , 8 , 13 , 16
analog integrated circuit device data 4 freescale semiconductor 33897/a/b/c/d/t internal block diagram internal block diagram figure 3. 33897/a/b/c/d/t simp lified internal block diagram co ntrol mode0 mode1 tx bus drvr bu s rcvr load sw itch wa ve sha pin g e n hvwu en tx data txd hv w u de t rxd rx data tim ers timer osc un der vo ltag e detect load bat cnt l gnd bus disable disable mode vbatt txd bus drvr bus rcvr hvwu enable waveshaping enable txd data disable hvwu detect rxd data mode control cntl* *cntl terminal is pres ent on 33897/a/c/t only. disable
analog integrated circuit device data freescale semiconductor 5 33897/a/b/c/d/t pin connections pin connections figure 4. 33897/a/b/ c/d/t pin connections table 2. pin definitions a functional description of each terminal can be found in the functional pin description section, beginning on page 13 . 33897/a/c/t terminal 33897b/d terminal pin name formal name definition 1, 7, 8, 14 8 gnd ground electrical common ground and heat removal. a good thermal path will also reduce the die temperature. 2 1 txd transmit data data input here will appear on the bus terminal. a logic [0] will assert the bus, a logic [1] will make the bus go to the recessive state. 3, 4 2, 3 mode0, mode1 mode control these pins control sleep mode, transmit level, and speed. they have weak pulldowns. 5 4 rxd receive data open drain output of the data on bus. a recessive bus = a logic [1], a dominant bus = logic [0]. an external pullup is required. 6, 13 ? nc no connect no internal connection to these pi ns. pin 13 can be connected to gnd to allow the use of the 14-terminal or 8-terminal device. (1) 9 ? cntl control provides a battery-level logic signal. 10 5 vbatt battery power input. an external diode is needed for reverse battery protection. 11 6 load load the external bus load resistor connec ts here to prevent bus pullup in the event of loss of module ground. 12 7 bus bus this terminal connects to the bus through external components. notes 1. module boards can be planned for the 14-terminal package and still use the 8-terminal package. gnd vbatt cntl gnd nc bus load gnd rxd nc gnd txd mode0 mode1 5 6 7 2 3 4 14 10 9 8 13 12 11 1 33897/a/c/t 2 3 4 8 7 6 5 1 1 2 4 3 8 7 5 6 gnd bus vbatt txd mode0 mode1 rxd load 33897b/d
analog integrated circuit device data 6 freescale semiconductor 33897/a/b/c/d/t electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings supply voltage v batt - 0.3 to 40 v input logic voltage v in - 0.3 to 7.0 v rxd pin voltage v rxd - 0.3 to 7.0 v cntl pin voltage (33897/a/c/t only) v cntl - 0.3 to 40 v esd voltage (2) human body model all pins except bus 33897/a/b/t 33897c/d bus terminal (all pkgs) machine model 33897/a/b 33897c/d/t v esd 2000 1500 4000 200 100 v thermal ratings ambient operating temperature (3) t a - 40 to 125 c junction operating temperature t j - 40 to 150 c storage temperature t stg - 55 to 150 c junction-to-ambient thermal resistance r ja 150 c/w peak package reflow temperature during reflow (4) , (5) t pprt note 5. c notes 2. esd testing is performed in accord ance with the human body model (c zap = 100 pf, r zap = 1500 ), machine model (c zap = 200 pf, r zap = 0 ). 3. when using the 8-terminal device, consider the power dissipation at a high operati ng voltage and maximum network loading at a mbient temperatures exceeding 85c. 4. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability meets pb-free requirem ents for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove prefix es/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data freescale semiconductor 7 33897/a/b/c/d/t electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltag es are relative to gnd unless otherwise noted. all positive currents are into the terminal. all negative currents are out of the terminal. characteristic symbol min typ max unit general quiescent current sleep 5.0 v v batt 13 v (6) 33897/a/b/c/d 33897t awake with transmitter disabled 5.0 v v batt 26.5 v awake with transmitter enabled 5.0 v v batt 26.5 v i qslp i qatdis i qaten ? ? ? ? 45 55 ? ? 60 75 4.0 9.0 a ma ma undervoltage shutdown v battuv 4.0 ? 5.0 v undervoltage hysteresis v uvhys 0.1 ? 0.5 v thermal shutdown (7) 5.0 v v batt 26.5 v t sd 150 ? 190 c thermal shutdown hysteresis (7) 5.0 v v batt 26.5 v t sdhys 10 ? 20 c logic i /o, mode0, mode1, txd, rxd logic input low level (mode0, mode1, and txd) 5.0 v v batt 26.5 v v il ? ? 0.8 v logic input high level (mode0, mode1, and txd) 5.0 v v batt 26.5 v v ih 2.0 ? ? v mode pin pulldown current (mode0 and mode1) pin voltage = 0.8 v, 5.0 v v batt 26.5 v i pd 10 ? 50 a receiver output low (rxd) i in = 2.0 ma, 5.0 v v batt 26.5 v v ol ? ? 0.45 v cntl (33897/a/c/t only) cntl output low i in = 5.0 a, 5.0 v v batt 26.5 v v olcntl ? ? 0.8 v cntl output high i out = 180 a, 5.0 v v batt 26.5 v v ohcntl v batt - 0.8 ? v batt v notes 6. after t cntlfdly 7. thermal shutdown causes the bus output driver to be disabled. guaranteed by characterization.
analog integrated circuit device data 8 freescale semiconductor 33897/a/b/c/d/t electrical characteristics static electrical characteristics load load voltage rise (8) normal speed and voltage mode, transmit high- voltage mode, transmit high-speed mode i in = 1.0 ma, 5.0 v v batt 26.5 v sleep mode i in = 7.0 ma 33897/t i in = 7.0 ma (9) 33897a/b/c/d loss of battery i in = 7.0 ma v ldrise ? ? ? ? ? ? ? ? 0.1 1.0 0.1 1.0 v load leakage during loss of module ground (10) 0.0 v v batt 18 v 33897/a/b/t 0.0 v v batt 18 v 33897c/d i ldleak 0.0 -10 ? ? - 90 10 a bus passive out bus leakage passive in 0.0 v v batt 26.5 v, -1.5 v v bus < 0 v active in 0.0 v v batt 26.5 v, 0 v < v bus 12.5 v bus leakage during loss of module ground (11) 0.0 v v batt 18 v 33897/a/b/t 0.0 v v batt 18 v 33897c/d i leak i lkai i blklog -5.0 -5.0 -10 0.0 ? ? ? ? 5.0 5.0 10 -90 a high-voltage wake-up mode output high voltage 12 v v batt 26.5 v, 200 r l 3332 33897/t 33897a/b/c/d 5.0 v v batt < 12 v, 200 r l 3332 v hvwuohf v hvwuoho 9.7 9.9 lesser of v bat - 1.5 or 9.7 ? ? 12.5 12.5 v batt v high-speed mode output high voltage 8.0 v v batt 16 v, 75 r l 135 v ohhs 4.2 ? 5.1 v normal mode output high voltage 6.0 v v batt 26.5 v, 200 r l 3332 5.0 v v batt < 6.0 v, 200 r l 3332 v nohf v noho 4.4 lesser of v batt - 1.6 or 4.4 ? ? 5.1 lesser of v batt or 5.1 v bus low voltage 5.0 v v batt 26.5 v, 200 r l 3332 v ol - 0.2 ? 0.2 v short circuit bus output current dominant state, 5.0 v v batt 26.5 v i bsc -350 ? - 150 ma notes 8. gmw3089v2.4 specifies the maximum load voltage rise to be 0.1 v whenever module battery is intact, including when in sleep mode. the maximum load voltage rise of 1.0 v in sleep mode is a gm-approv ed exception to gmw3089v2.4. 9. 33897a/b/c/d remove diode drop during sleep mode. 10. load terminal is at system ground voltage. 11. bus terminal is at system ground voltage table 4. static electrical characteristics (continued) characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltag es are relative to gnd unless otherwise noted. all positive currents are into the terminal. all negative currents are out of the terminal. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33897/a/b/c/d/t electrical characteristics static electrical characteristics bus (continued) input threshold awake 5.0 v v batt 26.5 v sleep 12 v v batt 26.5 v sleep 5.0 v v batt < 12 v v bia v bisf v biso 2.0 6.6 lesser of 6.6 v or v batt - 4.3 ? ? ? 2.2 7.9 lesser of 7.9 v or v batt - 3.25 v table 4. static electrical characteristics (continued) characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltag es are relative to gnd unless otherwise noted. all positive currents are into the terminal. all negative currents are out of the terminal. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33897/a/b/c/d/t electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltages are relative to gnd unless otherwise noted. all positive currents are into the terminal. all negative currents are out of the terminal. characteristic symbol min typ max unit bus normal speed rising output delay 200 r l 3332 , 1.0 s load time constants 4.0 s measured from txd = v il to v bus as follows: max time to v busmod = 3.7 v, 6.0 v v batt 26.5 v (12) min time to v busmod = 1.0 v, 6.0 v v batt 26.5 v (12) max time to v busmod = 2.7 v, v batt = 5.0 v (12) min time to v busmod = 1.0 v, v batt = 5.0 v (12) t dlynormro 2.0 ? 6.3 s normal speed falling output delay 200 r l 3332 , 1.0 s load time constants 4.0 s measured from txd = v ih to v bus as follows: max time to v busmod = 1.0 v, 6.0 v v batt 26.5 v (12) min time to v busmod = 3.7 v, 6.0 v v batt 26.5 v (12) max time to v busmod = 1.0 v, v batt = 5.0 v (12) min time to v busmod = 2.7 v, v batt = 5.0 v (12) t dlynormfo 1.8 ? 8.5 s high-speed rising output delay 75 r l 135 , 0.0 s load time constants 1.5 s, 8.0 v v batt 16 v measured from txd = v il to v bus as follows: max time to v bus = 3.7 v (13) min time to v bus = 1.0 v (13) t dlyhsro 0.1 ? 1.7 s high-speed falling output delay 75 r l 135 , 0.0 s load time constants 1.5 s, 8.0 v v batt 16 v measured from txd = v ih to v bus as follows: max time to v bus = 1.0 v (13) min time to v bus = 3.7 v (13) t dlyhsfo 0.04 ? 3.0 s notes 12. v busmod is the voltage at the busmod node in figure 7 , page 15 . 13. v bus is the voltage at the bus terminal in figure 8 , page 15 .
analog integrated circuit device data freescale semiconductor 11 33897/a/b/c/d/t electrical characteristics dynamic electrical characteristics bus (continued) high-voltage rising output delay 200 r l 3332 , 1.0 s load time constants 4.0 s measured from txd=v il to v bus as follows: max time to v busmod = 3.7 v, 6.0 v v batt 26.5 v (14) min time to v busmod = 1.0 v, 6.0 v v batt 26.5 v (14) max time to v busmod = 9.4 v, 12.0 v v batt 26.5 v (14) t dlyhvro 2.0 2.0 2.0 ? ? ? 6.3 6.3 18 s high-voltage falling output delay 200 r l 3332 , 1.0 s load time constants 4.0 s, 12.0 v v batt 26.5 v measured from txd=v ih to v bus as follows: max time to v busmod = 1.0 v (14) min time to v busmod = 3.7 v (14) t dlyhvfo 1.8 1.8 ? ? 14 14 s receiver rxd receive delay time (5.0 v v batt 26.5 v) awake t rdly 0.2 ? 1.0 s receive delay time (bus rising to rxd falling, 5.0 v v batt 26.5 v) sleep t rdlysl 10 ? 70 s cntl cntl falling delay time (5.0 v v batt 26.5 v) (33897/a/c/t only) t cntlfdly 300 ? 1000 ms notes 14. v busmod is the voltage at the busmod node in figure 7 , page 15 . table 5. dynamic electrical characteristics (continued) characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltages are relative to gnd unless otherwise noted. all positive currents are into the terminal. all negative currents are out of the terminal. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33897/a/b/c/d/t electrical characteristics timing diagrams timing diagrams figure 5. txd, bus and rxd waveforms in normal mode figure 6. txd, bus and rxd waveforms in high speed mode * v busmod is the voltage at the busmod node in figure 7. txd bus rxd v il v ih v busmod t dlynormfo v nohf v bia v il v bia t rdly t dlynormro t rdly v ih v busmod * * * v bus is the voltage at the bus terminal in figure 8. txd bus rxd t dlyhsfo t dlyhsro v ih v il v bus * v bia v nohf t rdly v ih v bia v bus * v il t rdly
analog integrated circuit device data freescale semiconductor 13 33897/a/b/c/d/t functional description introduction functional description introduction the 33897 series is intended for use as a physical layer device in a single wire can communications bus. communications takes place from a single terminal over a single wire using a common ground for a current return path. two data rates are available, with the high rate used for factory or assembly line communications and the lower for actual system communications w here the radiated emi of the higher rate could be an issue. two pins control the mode of operation (sleep, low-speed, high-speed, and high-voltage wake-up). functional pin description the 33897 series is intended to be used with an mcu to control its operation and to pr ocess and generate the data for the bus. ground pins (33897/a/c/t) the four ground pins are not only for electrical conduction, their number and lo cations at each of the four corners serve also to remove heat from the ic. the biggest benefit of this is obtained by putting a lot of copper on the pcb in this area and, if ground is an internal layer, by adding numerous plated-through connecti ons to it with the largest diameter holes the layout can use. txd data the data driven onto the swcan bus is inverted from the txd terminal. a ?1? driven on txd will result in an undriven (recessive) state (bus at near zero volts). when the txd terminal is low, the output goes to a driven state. the voltage and waveshaping in the driven state is determined by the levels on the mode0 and mode1 pins (refer to table 6 ). mode control the mode pins control the tr ansmitter filtering and bus voltage and the ic sleep mode operation. table 6 shows the mode versus the logic levels on mode0 and mode1. the mode0 and mode1 pins have a weak pulldown in the ic so that in case the pins are not driven, the device will enter the sleep mode. this is usually the situation as the mcu comes out of reset, before the driving signals have been configured as outputs. rxd data the data received on the bus is translated to logic levels on this terminal. this terminal is a logic high when the bus is in the recessive stat e (near zero volts) and is logic low when the bus is in either the normal or high-voltage dominant state. this is an open-drain type of output that requires an external resistor to pull it up. when the device is in sleep mode, the output will be off unless a high-voltage wake-up level is detected on the bus. if the wake-up level is detected, the output will be driven by the data on the bus. if the level of the data returns to normal level, the output will return to off after a short delay unless a non-sleep mode condition is set by the mcu. load switch this switch is on in all operating modes unless a loss of ground is detected. if this happens, the switch is opened and the resistor normally attached to its terminal will no longer pass current to or from the bus. cntl output (33897/a/c/t only) this logic level signal is used to control a v cc regulator. when the output is low, the v cc regulator is expected to shutdown. this is normally used to shut down the mcu and all the devices powered by v cc when the ic is in sleep mode. this is done to save power. when the part is taken out of the sleep mode by the higher-than-normal bus voltage, this terminal is asserted high and the v cc regulator brings its output up to the regulated level. this starts the mcu, which controls the mode of the ic. the mcu must change the mode signals to non-sleep mode levels in order to keep this terminal from going low. there is a delay to allow the mcu to fully wake up and take control after the high-voltage signaling is removed before the level on th is output returns low. after a delay time, even if the bus is at high voltage, the ic will return to sleep mode if both mode pins are low. vbatt input this power input is not re verse battery protected and should use an external diode to protect it from damage owing to reverse battery if this pr otection is desired. the voltage drop of the diode must be tak en into consideration when the operating range of the system is being determined. this table 6. mode control logic levels logic level operation mode0 mode1 0 0 sleep mode 0 1 high voltage wake-up mode 1 0 high speed mode 1 1 normal mode
analog integrated circuit device data 14 freescale semiconductor 33897/a/b/c/d/t functional description functional block diagram components diode is generally used to protect the entire module from reverse battery and should be selected accordingly. bus i /o this input / output may require electrostatic discharge (esd) and /or emi external circuitry. a set of components is shown in the simplified application diagrams on page 16 of this datasheet. the value of the capacitor should be adjusted downward in direct proportion to the added capacitance of the esd or emi circuits. the series resistance of the inductor should be kept below 3.5 to prevent its voltage drop from significantly degrading system noise margins. functional block diagram components timer osc this circuit generates a 500 khz signal to be used for internal logic. it is the reference for some of the required delays. timers this circuit contains the timing logic used to hold the cntl active for the required time after the conditions for sleep mode have been met. it is also used to keep the txd driver active for a period of time after it has generated a passive level on the bus. mode control this circuit contains the control logic for the various operating modes and conditions required for the ic. bus rcvr this circuit translates the levels on the bus terminal to a cmos level indicating the presence of a logic [0] or a logic [1]. it also determines the presence of a high-voltage wake-up (hvwu) signal that is passed to mode control and timers circuits. an analog filter is used to ?de-glitch? the high- voltage wake-up signal and prev ent false exits from the sleep mode. txd bus drvr this circuit drives the bus. it can drive it with the higher voltage wake-up signals when enabled by the mode control circuit. it can also provide waveshaping for reduced emi or not provide it for the higher data rate mode. the actual data is received on txd at cmos logi c levels, then translated by this circuit to the necessary operating voltages. undervoltage detect this circuit monitors internal operating voltage to assure proper operation of the part. if a low-voltage condition is detected, it sends a signal to disable the bus rcvr and txd bus drvr circuits. this prevents incorrect data from being put on the bus or sent to the mcu. load switch the load switch provides a pat h for an external resistor connected to the bus to be connected to ground. when a loss of ground is detected, this switch is opened to prevent the current that would normally be flowing to the ground from the module from going back thr ough the load resistor and raising the bus level. the circuit is opened when the voltage between gnd and vbatt become s too low as would be the case if module ground were lost.
analog integrated circuit device data freescale semiconductor 15 33897/a/b/c/d/t bus loading parameters functional block diagram components bus loading parameters figure 7. transmitter delays in normal and transmit high-voltage wake-up modes figure 8. transmitter delays in transmit high-speed mode 47 h 1.0 k c nom = 100 pf + (n -1) 220 pf r = 6.49 k (n -1) 33897 6.49 k bus load gnd 100 pf v batt note: the letter ?n? represents the number of nodes in the system. busmod 130 c nom = (n) 220 pf r = 6.49 k 33897 6.49 k bus load gnd (n -1) note: the letter ?n? represents the number of nodes in the system.
analog integrated circuit device data 16 freescale semiconductor 33897/a/b/c/d/t typical applications typical applications the 33897/a/c/t can be used in applications where the module includes a regulator that has the capability of going into sleep mode by having an enable terminal. see figure 9 . when the module?s regulator is in sleep mode, the module is turned off. the module waits for a defined wake-up voltage level on the bus. this wake-up voltage will activate the control line, which enables the regulator and turns the module back on. this 33897/a/c/t feature allows the module to be more energy efficient since the current consumption is significantly lowered when it goes into sleep mode. figure 9. 33897/a/c/t ty pical application schematic the 33897b/d do not have a control terminal to enable the module?s regulator. see figure 10 . the 33897b/d can be used in applications where board space is limited and there is no need for the module to have control over its regulator via the transceiver. figure 10. 33897b/d typical application schematic gnd cntl vbatt load bus rxd mode0 txd voltage regulator 33897/a/c/t en v cc mcu 10 k 2.7 k 6.49 k 1.0 k battery 47 h swc bus v cc power mode1 47 pf 100 pf source 4.7 f 4 100 nf gnd vbatt load bus rxd mode0 txd 33897b/d v cc mcu 10 k 2.7 k 6.49 k 1.0 k battery 47 h swc bus v cc mode1 47 pf 100 nf 100 pf 4.7 f
analog integrated circuit device data freescale semiconductor 17 33897/a/b/c/d/t packaging package dimensions packaging package dimensions important : for the most current package revision, visit www.freescale.com and perform a keyword search on the ?98a? drawing number below. d suffix ef (pb-free) suffix 14-terminal soicn plastic package 98asb42565b issue h
analog integrated circuit device data 18 freescale semiconductor 33897/a/b/c/d/t packaging package dimensions (continued) package dimensions (continued) ef (pb-free) suffix 8-terminal soicn plastic package 98asb42564b issue u
analog integrated circuit device data freescale semiconductor 19 33897/a/b/c/d/t revision history revision history revision date description of changes 9.0 5/2005 ? converted to freescale format ? added a & b versions ? updated device variation table, and note ?* recommended device for all new designs? ? added ef (pb-free) devices, and higher soldering temperature 10.0 8/2005 ? implemented revision history page ? updated simplified application diagrams ? updated typical application schematic 11.0 12/2005 ? added 33897c and d versions and timing diagrams 12.0 1/2006 ? updated table 4, static electrical c haracteristics - load and bus parameters ? updated ordering information. 13.0 6/2006 ? removed ?unless otherwise not ed? from static electrical characteristics & dynamic electrical characteristics table introductions 14.0 8/2006 ? added part numbers mc33897td and mc33897tef to ordering information on page 1. ? added 33897t to table 1, device variations on page 3, referencing electrical changes per errata mc33897ter, revision 3 and specifying esd variations 15.0 10/2006 ? removed part numbers mc33897td/r2, mc33897tef/r2, mc33897clef/r2, pc33897clef/r2, mc33897dlef/r2, and pc33897dlef/r2 ? added part numbers mcz33897ef/r2, mcz33897tef/r2, mcz33897aef/r2, mcz33897cef/r2, mcz33897bef/r2, and mcz33897def/r2 to the ordering information block on page 1. ? updated device variations on page 3 for ?t? suffix products ? split out human body model on page 6 to differentiate between t and non-t versions ? added undervoltage hysteresis on page 7 ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 6 . added note with instructions to obtain this information from www.freescale.com . 16.0 6/2007 ? removed watermark, ?advance information? from page 1.
mc33897 rev. 16.0 6/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006 - 2009. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp .

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